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ADVANCE INFORMATION
GALVANTECH, INC. SYNCHRONOUS CACHE TAG SRAM PIPELINED OUTPUT
FEATURES
* * * * * * * * * * * * * * * * * * * Fast match times: 3.5, 3.8, 4.0 and 4.5ns Fast clock speed: 166, 150, 133, and 100MHz Fast OE# access times: 3.5, 3.8, 4.0 and 5.0ns Pipelined data comparator Data input register load control by DEN# Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V -5% and +10% core power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/O's Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs JTAG boundary scan BYTE WRITE ENABLE and GLOBAL WRITE control Three chip enables for depth expansion and address pipeline Address, data and control registers Internally self-timed WRITE CYCLE Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low profile 119 lead, 14mm x 22mm BGA (Ball Grid Array) and JEDEC standard 100 pin TQFP packages
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
256K x 18 SRAM
+3.3V SUPPLY WITH CLOCKED REGISTERED INPUTS
GENERAL DESCRIPTION
The Galvantech Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE#), depth-expansion chip enables (CE2# and CE2), burst control inputs (ADSC#, ADSP#, and ADV#), write enables (WEL#, WEH#, and BWE#), global write (GW#), and data input enable (DEN#). Asynchronous inputs include the burst mode control (MODE), the output enable (OE#) and the match output enable (MOE#). The data outputs (Q) and match output (MATCH), enabled by OE# and MOE# respectively, are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Data inputs are registered with data input enable (DEN#) and chip enable pins (CE#, CE2 and CE2#). The outputs of the data input registers are compared with data in the memory array and a match signal is generated. The match output is gated into a pipeline register and released to the match output pin at the next rising edge of clock (CLK). Address, data inputs, and write controls are registered onchip to initiate self-timed WRITE cycle. WRITE cycles can be one to two bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL# controls DQ1-DQ9. WEH# controls DQ10DQ18. WEL#, and WEH# can be active only with BWE# being LOW. GW# being LOW causes all bytes to be written. The GVT71256T18 operates from a +3.3V power supply with output power supply being +2.5V or +3.3V. All inputs and outputs are LVTTL compatible. The device is ideally suited for address tag RAM for up to 8MB secondary cache.
OPTIONS
* Timing 3.5ns access/6.0ns cycle 3.8ns access/6.7ns cycle 4.0ns access/7.5ns cycle 4.5ns access/10ns cycle Packages 119-lead BGA 100-pin TQFP
MARKING
-6 -6.7 -7.5 -10 B T
*
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
Rev. 8/98
Galvantech, Inc. reserves the right to change products or specifications without notice.
ADVANCE INFORMATION
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
HIGHER BYTE WRITE
WEH# BWE#
D
Q
D
LOWER BYTE WRITE
Q
WEL# GW# CE# CE2 CE2# ZZ OE# ADSP# MOE# Power Down Logic Latch
D
Q
lo byte write hi byte write
ENABLE
D
Q
D
Q
D
Q
MATCH
Compare
DEN# Latch CLK A ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic 16 Address Register
Input Register
OUTPUT REGISTER
256K x 9 x 2 SRAM Array
Output Buffers
D
Q
DQ1DQ18
NOTE:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
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Rev. 8/98
ADVANCE INFORMATION
GALVANTECH, INC.
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
PIN ASSIGNMENTS (TOP VIEW)
1 A B C D E F G H J K L M N P R T U
VCCQ NC NC DQ10 NC VCCQ NC DQ13 VCCQ NC DQ15 VCCQ DQ17 NC NC NC VCCQ
2 A
CE2
3 A A A
VSS VSS VSS WEH# VSS NC VSS VSS VSS VSS VSS MODE A TDI
4
ADSP# ADSC# VCC NC CE# OE# ADV#
5 A A
A VSS VSS VSS VSS VSS NC VSS WEL# VSS VSS VSS NC A TDO
6
A CE2# A DQ9 NC DQ7 NC DQ5 VCC NC DQ3
MATCH
7
VCCQ NC NC NC DQ8 VCCQ DQ6 NC VCCQ DQ4 NC VCCQ DEN# DQ1 NC ZZ VCCQ NC NC NC VCCQ VSSQ NC NC DQ10 DQ11 VSSQ VCCQ DQ12 DQ13 NC VCC NC VSS DQ14 DQ15 VCCQ VSSQ DQ16 DQ17 DQ18 NC VSSQ VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99
A A CE# CE2 NC NC WEH# WEL# CE2# VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A
98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
A
NC DQ11 NC DQ12 NC VCC DQ14 NC DQ16 NC DQ18
GW#
VCC CLK NC BWE#
100-pin TQFP
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A1 A0
VCC NC TCK
DQ2 MOE# A A NC
A
A TMS
A NC NC VCCQ VSSQ NC DQ9 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ MATCH DEN# MOE#
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TOP VIEW 119 LEAD BGA
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Rev. 8/98
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
Galvantech, Inc. reserves the right to change products or specifications without notice.
ADVANCE INFORMATION
GALVANTECH, INC.
PIN DESCRIPTIONS
BGA PINS
4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 5L 3G
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
TQFP PINS
37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 93 94
SYMBOL
A0 A1 A
TYPE
Input-
DESCRIPTION
Addresses: These inputs are registered and must meet the Synchronous setup and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. InputByte Write Enables: A byte write enable is LOW for a DQ1-DQ9. WEH# controls DQ10-DQ18. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE# being LOW.
WEL# WEH#
Synchronous WRITE cycle and HIGH for a READ cycle. WEL# controls
4M
87
BWE#
Input-
Write Enable: This active LOW input gates byte write the rising edge of CLK.
Synchronous operations and must meet the setup and hold times around
4H
88
GW#
Input-
Global Write: This active LOW input allows a full 18-bit and must meet the setup and hold times around the rising edge of CLK.
Synchronous WRITE to occur independent of the BWE# and WEn# lines
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge.
Synchronous enables, write control and data input enable control input on
4E 6B 2B 4F 4G
98 92 97 86 83
CE# CE2# CE2 OE# ADV#
InputInputinputInput Input-
Chip Enable: This active LOW input is used to enable the Chip Enable: This active LOW input is used to enable the Chip enable: This active HIGH input is used to enable the Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control cycle (no address advance).
Synchronous device and to gate ADSP#. Synchronous device. Synchronous device.
Synchronous the internal burst counter. A HIGH on this pin generates wait
4A
84
ADSP#
Address Status Processor: This active LOW input, along Synchronous with CE# being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. InputAddress Status Controller: This active LOW input causes external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
Synchronous device to be de-selected or selected along with new
Input-
4B
85
ADSC#
3R
31
MODE
InputStatic Input-
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Snooze: This active HIGH input puts the device in low this input has to be either LOW or NC (No Connect).
7T
64
ZZ
Asynchronous power consumption standby mode. For normal operation,
7N 6M
52 53
DEN# MATCH
InputOutput
Data Input Enable: This active LOW input is used to control Match Output: MATCH will be HIGH if data in the data input registers match the data stored in the memory array, assuming MOE# being LOW. MATCH will be LOW if data do not match. Match Output Enable: This active LOW asynchronous input enables the MATCH output drivers. Data Inputs/Outputs: Input data must meet setup and hold times around the rising edge of CLK. IEEE 1149.1 test output. LVTTL-level output.
Synchronous the update of data input registers.
6P
51
MOE# DQ1-DQ18
Input Input/ Output Output
7P, 6N, 6L, 7K, 6H, 7G, 6F, 58, 59, 62, 63, 68, 69, 72, 7E, 6D, 1D, 2E, 2G, 1H, 73, 74, 8, 9, 12, 13, 18, 19, 2K, 1L, 2M, 1N, 2P 22, 23, 24 5U 42
TDO
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PIN DESCRIPTIONS (continued)
BGA PINS
2U 3U 4U 4C, 2J, 4J, 6J, 4R 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
TQFP PINS
38 39 43 15, 41,65, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77
SYMBOL
TMS TDI TCK VCC VSS
TYPE
Input
DESCRIPTION
IEEE 1149.1 test inputs. LVTTL-level inputs.
Supply Ground
Power Supply: +3.3V -5% and +10% Ground: GND.
VCCQ NC
I/O Supply -
Output Buffer Supply: +2.5V (from 2.375V to VCC) No Connect: These signals are not internally connected.
1B, 7B, 1C, 7C, 2D, 4D, 1-3, 6, 7, 14, 16, 25, 287D, 1E, 6E, 2F, 1G, 6G, 30, 56, 57, 66, 75, 78, 79, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 95, 96 4L, 7L, 2N, 1P, 1R, 5R, 7R, 1T, 4T, 6U
BURST ADDRESS TABLE (MODE = NC/VCC)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A00 A...A11 A...A10
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A10 A...A01 A...A00
BURST ADDRESS TABLE (MODE = GND)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A10 A...A11 A...A00
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A00 A...A01 A...A10
PARTIAL TRUTH TABLE FOR MATCH
OPERATION E# WE# DEN# MOE## OE# MATCH DQ
READ Cycle WRITE Cycle Fill WRITE Cycle COMPARE Cycle Deselected Cycle (MATCH Out) Deselected Cycle
L L L L H H
H L L H X X
X L H L X X
X X X L L H
L H H H X X
Output H High-Z
Q D High-Z D High-Z High-Z
Note:
1. 2. 3. 4. 5.
X means "don't care." H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP# is HIGH and
ADSC# is LOW.
E# =L is defined as CE#=LOW and CE2#=LOW and CE2=HIGH. E# =H is defined as CE#=HIGH or CE2#=HIGH or CE2=LOW. WE# is defined as [BWE# + WEL#*WEH#]*GW#. All inputs except OE# and MOE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time for OE# and staying HIGH throughout the input data hold time. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
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TRUTH TABLE
OPERATION ADDRESS USED CE# CE2#
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
CE2
ADSP# ADSC#
ADV#
WRITE#
OE#
CLK
DQ
Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst
None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current
H L L L L L L L L L X X H H X H X X H H X H
X X H X H L L L L L X X X X X X X X X X X X
X L X L X H H H H H X X X X X X X X X X X X
X L L H H L L H H H H H X X H X H H X X H X
L X X L L X X L L L H H H H H H H H H H H H
X X X X X X X X X X L L L L L L H H H H H H
X X X X X X X L H H H H H H L L H H H H L L
X X X X X L H X L H L H L H X X L H L H X X
L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Note:
1. 2. 3. 4. 5. 6. 7.
X means "don't care." H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# + WEL#*WEH#]*GW# equals LOW. WRITE# = H means [BWE# + WEL#*WEH#]*GW# equals HIGH. It is assumed in this truth table that DEN# is LOW. WEL# enables write to DQ1-DQ9. WEH# enables write to DQ10-DQ18. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. Suspending burst generates wait cycle. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time for OE# and staying HIGH throughout the input data hold time. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE FOR READ/WRITE
FUNCTION READ READ WRITE one byte WRITE all bytes WRITE all bytes Note: 1. GW# H H H H L BWE# H L L L X WEH# X H L L X WEL# X H H L X
X means "don't care." H means logic HIGH. L means logic LOW. It is assumed in this truth table that chip is selected and ADSP# is HIGH along with DEN# being LOW.
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ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN ...........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +150o Junction Temperature .....................................................+150o Power Dissipation ............................................................1.0W Short Circuit Output Current ..........................................50mA
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
*Stresses greater than those listed uunder "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0oC Ta
70C; VCC = 3.3V -5% and +10% unless otherwise noted)
CONDITIONS
Data Inputs (DQxx) All Other Inputs
DESCRIPTION
Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage I/O Supply Voltage
SYMBOL
VIHD VIH VIl ILI ILO VOH VOH VOL VCC VCCQ
MIN
1.7 1.7 -0.3 -2 -2 2.4 1.7
MAX
VCC+0.3 4.6 0.8 2 2
UNITS
V V V uA uA V V
NOTES
1,2 1,2 1, 2 14 1, 11 1, 11 1, 11 1 1
0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0mA at VCCQ=3.135V IOH = -4.0mA at VCCQ=2.375V IOL =8.0mA
0.4 3.135 2.375 3.6 VCC
V V V
DESCRIPTION
Power Supply Current: Operating CMOS Standby
CONDITIONS
Device selected; all inputs < VILor > VIH;cycle time > tKC MIN; VCC =MAX; outputs open Device deselected; VCC = MAX; all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH ; all inputs static; VCC = MAX; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = MAX; CLK cycle time > tKC MIN
SYM
Icc
TYP
100
-6
310
- 6.7
275
- 7.5
250
- 10
190
UNITS NOTES
mA 3, 12, 13
ISB2
5
10
10
10
10
mA
12,13
TTL Standby
ISB3
10
20
20
20
20
mA
12,13
Clock Running
ISB4
40
80
70
60
50
mA
12,13
THERMAL CHARACTERISTICS
DESCRIPTION
Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case
CONDITIONS
Still air, soldered on 4.25 x 1.125 inch 4-layer PCB
SYMBOL
JA JC
BGA TYP
19 9
TQFP TYP
25 9
UNITS
o o
NOTES
C/W C/W
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AC ELECTRICAL CHARACTERISTICS
(Note 5) (0oC
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
TA 70oC; VCC = 3.3V -5% and +10%)
-6 166MHz
SYM MIN MAX
DESCRIPTION
Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to MATCH valid Clock to output invalid Clock to MATCH invalid Clock to output in Low-Z Clock to output in High-Z OE to output valid MOE to MATCH valid OE to output in Low-Z MOE to MATCH in Low-Z OE to output in High-Z MOE to MATCH in High-Z Setup Times Address, Controls and Data In Hold Times Address, Controls and Data In
t t t t t t t t t t t t
- 6.7 150MHz
MIN MAX
- 7.5 133MHz
MIN MAX
- 10 100MHz
MIN MAX UNITS NOTES
KC KF KH KL
6.0 166 1.5 1.5 3.5 3.5 1.5 1.5 1.5 1.5 3.5 3.5 3.5 0 0 3.5 3.5 1.5 0.5
6.7 150 1.5 1.5 3.8 3.8 1.5 1.5 1.5 1.5 3.8 3.8 3.8 0 0 3.8 3.8 1.5 0.5
7.5 133 2.0 2.0 4.0 4.0 1.5 1.5 1.5 1.5 4.0 4.0 4.0 0 0 4.0 4.0 2.0 0.5
10 100 2.0 2.0 4.5 4.5 1.5 1.5 1.5 1.5 5.0 5.0 5.0 0 0 5.0 5.0 2.0 0.5
ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 6,7 4, 6,7 9 9 4, 6,7 4, 6,7 4, 6,7 4, 6,7 10 10
f t
t
KQ
KM
KQX
KMX
KQLZ OEQ
KQHZ
t
MOEM
t
OELZ
MOELZ
t
OEHZ
MOEHZ S
H
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 3.3V
SYMBOL
CI CO
TYP
4 7
MAX
5 8
UNITS
pF pF
NOTES
4 4
TYPICAL OUTPUT BUFFER CHARACTERISTICS
OUTPUT HIGH VOLTAGE
VOH (V) -0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 3.4
PULL-UP CURRENT
(m) in (m) ax -38 -38 -38 -26 -20 0 0 0 0 -105 -105 -105 -83 -70 -30 -10 0 0
OUTPUT LOW VOLTAGE
VOL (V) -0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4
PULL-DOWN CURRENT
L(m) in L(m) ax 0 0 10 20 31 40 40 40 40 0 0 20 40 63 80 80 80 80
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AC TEST CONDITIONS Input pulse levels Input slew rate Output rise and fall times(max) Input timing reference levels Output reference levels Output load 0V to 2.5V 1.0V/ns 1.8ns 1.25V 1.25V See Figures 1and 2
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
OUTPUT LOADS
DQ Z0 = 50 50 Vt = 1.25V Fig. 1 OUTPUT LOAD EQUIVALENT +2.5v 1,667 DQ 1,538 5 pF 30 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +6.0V for t tKC /2. VIL -2.0V for t tKC /2
14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of +30 A. 15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.
Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. At any given temperature and voltage condition, tKQHZ is less than tKQLZ, tOEHZ is less than tOELZ and tMOEHZ is less than tMOELZ. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. OE# is a "don't care" after a write cycle begins To prevent bus contention, OE# should be negated prior before the start of write cycle.
8.
9.
10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table. 11. AC I/O curves are available upon request. 12. "Device Deselected" means the device is in POWER -DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13. Typical values are measured at 3.3V, 25oC and 20ns cycle time.
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GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
READ TIMING WITH BURST FEATURE
tKC t
KL
CLK
t
S
t
KH
ADSP#
t
H
ADSC#
t
S
ADDRESS WEL#, WEH#, BWE#, GW# CE# (See Note)
A1
t
A2
H
t
S
ADV#
t
H
OE#
tKQ tKQLZ tOELZ t
OEQ Q(A2)
tKQ
DQ
Q(A1)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Note: (1) CE# active in this timing diagram means that all chip enables CE#, CE2# and CE2 are active. (2) In this timing diagram, it is assumed that DEN# is tied to LOW (VSS).
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GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
WRITE TIMING WITH BURST FEATURE
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS WEL#, WEH#, BWE# GW# CE# (See Note)
A1
tH
A2
A3
tS
ADV#
tH
OE#
tOEHZ tKQX
DQ
Q
D(A1)
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Note: (1) CE# active in this timing diagram means that all chip enables CE#, CE2# and CE2 are active. (2) In this timing diagram, it is assumed that DEN# is tied to LOW (VSS).
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CLK
tS
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
READ/WRITE TIMING WITH BURST FEATURE
ADSP#
tH
ADSC#
tS
ADDRESS WEL#, WEH#, BWE#, GW# CE# (See Note) ADV#
A1
A2
tH
A3
A4
A5
OE#
DQ
Q(A1) Single Reads
Q(A2)
D(A3) Single Write
Q(A4)
Q(A4+1) Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
Note: (1) CE# active in this timing diagram means that all chip enables CE#, CE2# and CE2 are active. (2) In this timing diagram, it is assumed that DEN# is tied to LOW (VSS).
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GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
READ/WRITE TIMING WITHOUT BURST FEATURE
tKH tKC tKL
CLK
tS
ADDRESS
A1
A2
tH
A3
A4
A5
A6
A7
A8
WE# CE# (See Note) DEN#
tOEQ tOEHZ
OE#
tOELZ tKQLZ tKQ tKQX
tKQHZ
DQ
Q(A1)
Q(A2)
Q(A3)
Q(A4)
D(A5)
D(A6)
D(A7)
D(A8)
Reads
Writes
Note: (1) CE# active in this timing diagram means that all chip enables CE#, CE2# and CE2 are active. (2) In this timing diagram, it is assumed that burst feature is not used and therefore ADSP# is tied to HIGH (VCC) and ADSC# is tied to LOW (VSS). The logic state of ADV# is a "Don't Care". (3) In this timing diagram, it is assumed that WE# = [BWE# + WEL#*WEH#]*GW#.
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GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
COMPARE/FILL WRITE TIMING
tKH tKC tKL
CLK
tS
ADDRESS
A1
tH
A1
A2
WE# CE# (See Note) DEN#
OE#
DQ
D(A1)
tMOEHZ t
D(A2)
tMOEM
KM
MOE#
tMOELZ
MATCH HIGH CHIP DESELECTED
MATCH
tKMX
MISS
FILL WRITE
HIT
Note: (1) CE# active in this timing diagram means that all chip enables CE#, CE2# and CE2 are active. (2) In this timing diagram, it is assumed that burst feature is not used and therefore ADSP# is tied to HIGH (VCC) and ADSC# is tied to LOW (VSS). The logic state of ADV# is a "Don't Care". (3) In this timing diagram, it is assumed that WE# = [BWE# + WEL#*WEH#]*GW#.
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IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
OVERVIEW
This device incorporates a serial boundary scan access port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using LVTTL/LVCMOS logic level signaling.
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 3, TAP Controller State Diagram). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the most significant bit (MSB) of any register. (See Figure 4.)
TDO - TEST DATA OUT (OUTPUT)
The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 3, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 4.)
PERFORMING A TAP RESET
The TAP circuitry does not have a reset pin (TRST#, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state.
DISABLING THE JTAG FEATURE
It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device.
TEST ACCESS PORT (TAP) REGISTERS
OVERVIEW
The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins.
TEST ACCESS PORT (TAP)
TCK - TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.
TMS - TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
INSTRUCTION REGISTER
The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the
TDI - TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is
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controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path.
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM TAP CONTROLLER INSTRUCTION SET
OVERWIEW
There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables.
BYPASS REGISTER
The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed.
BOUNDARY SCAN REGISTER
The Boundary scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 54 bits in the case of the TAG device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit's position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state.
INDENTIFICATION (ID) REGISTER
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into ShiftDR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon powerup and at any time the TAP controller is placed in the testlogic reset state.
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SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state.
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
1
TEST-LOGIC RESET 0
0
REUN-TEST/ IDLE
1
SELECT DR-SCAN 0
1
SELECT IR-SCAN 0 1 CAPTURE-IR 0
1
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device's input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command.
1
CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 1 0
SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
0
1
0
0
EXIT2-DR 1 UPDATE-DR 1 0
Note: The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Figure 3 TAP CONTROLLER STATE DIAGRAM
0
Bypass Register
2 1 0
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
TDI
Selection Circuitry
Instruction Register
31 30 29
...
Selection Circuitry
0
TDO
2
1
Identification Register
x
.
....
2
1
0
Boundary Scan Register*
TDI
RESERVED
Do not use these instructions. They are reserved for future use.
TDI
TAP CONTROLLER
*X = 53 for this device.
Figure 4 TAP CONTROLLER BLOCK DIAGRAM
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TAP AC TEST CONDITIONS Input pulse levels Iutput rise and fall times Input timing reference levels Output reference levels Output load termination supply voltage VSS to 3.0V 1ns 1.5V 1.5V 1.5V
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM TAP OUTPUT LOADS
TDO Z0 = 50 50 Vt = 1.5V Figure 5 TAP AC OUTPUT LOAD EQUIVALENT 20 pF
TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(20oC Tj 110C; VCC = 3.3V -0.2V and +0.3V unless otherwise noted)
DESCRIPTIOPN
Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current LVCMOS Output Low Voltage LVCMOS Output High Voltage LVTTL Output Low Voltage LVTTL Output High Voltage 0V < VIN < VCC Output disabled, 0V < VIN < VCCQ IOLC = 100uA IOHC = 100uA IOLT = 8.0mA IOHT = 8.0mA
CONDITIONS
SYMBOL
VIH VIl ILI ILO VOLC VOHC VOLT VOHT
MIN
2.0 -0.3 -5.0 -5.0
MAX
VCC + 0.3 0.8 5.0 5.0 0.2
UNITS
V V uA uA
NOTES
1, 2 1, 2
1, 3 1, 3 1 1
VCC - 0.2 0.4 2.4
NOTE:
1. 2. All voltages referenced to VSS (GND). Overshoot: VIH(AC) VCC + 1.5V for t tKHKH/2. Undershoot: VIL(AC) -0.5V for t tKHKH/2 Power-up: VIH +3.6V and VCC 3.135V and VCCQ 1.4V for t 200ms During normal operation, VCCQ must not exceed VCC. Control input signals (such as GW#, ADSC#, etc.) may not have pulse widths less than tKHKL (MIN). This parameter is sampled.
3.
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GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM TAP TIMING
tTHTH
t
THTL
t
TLTH
TEST CLOCK (TCK)
tMVTH tTHMX
TEST MODE SELECT (TMS)
tDVTH tTHDX
TEST DATA IN (TDI)
tTLQV tTLQX
TEST DATA OUT (TDO)
TAP AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2) (20oC Tj 110C; VCC = 3.3V -0.2V and +0.3V)
DESCRIPTION Clock
Clock cycle time Clock frequency Clock HIGH time Clock LOW time
t t t
SYM
MIN
MAX
UNITS
THTH
f
20 50 8 8 0 10 5 5 5 5 5 5
ns MHz ns ns ns ns ns ns ns ns ns ns
TF
THTL TLTH
Output Times
TCK LOW to TDO unknown TCK LOW to TDO valid TDI valid to TCK HIGH TCK HIGH to TDI invalid
tTLQX tTLQV tDVTH tTHDX
Setup Times
TMS setup Capture setup
tMVTH tCS
Hold Times
TMS hold Capture hold
t
THMX
t
CH
NOTE:
1.
t
CS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in Figure 5.
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IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD REVISION NUMBER (31:28) DEVICE DEPTH (27:23) DEVICE WIDTH (22:18) RESERVED (17:12) GALVANTECH JEDEC ID CODE (11:1) ID Register Presence Indicator (0) BIT PATTERN XXXX 00110 00011 XXXXXX 00011100100 1
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
DESCRIPTION Reserved for revision number. Defines depth of 256K words. Defines width of x18 bits. Reserved for future use. Allows unique identification of DEVICE vendor. Indicates the presence of an ID register.
SCAN REGISTER SIZES
REGISTER NAME BIT SIZE
Instruction Bypass ID Boundary Scan
3 1 32 54
INSTRUCTION CODES
Instruction EXTEST
IDCODE SAMPLE-Z RESERVED SAMPLE/PRELOAD
RESERVED RESERVED BYPASS
Code Description 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. This instruction is not IEEE 1149.1-compliant. 001 Preloads ID register with vendor ID code and places it between TDI and TDO. This instruction does not affect device operations. 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. 011 Do not use these instructions; they are reserved for future use. 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This instruction does not affect device operations. This instruction does not implement IEEE 1149.1 PRELOAD function and is therefore not 1149.1-compliant. 101 Do not use these instructions; they are reserved for future use. 110 Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations.
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BOUNDARY SCAN ORDER
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SINGAL NAME TQFP BUMP ID
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 GW# CLK CE2# WEL# WEH# CE2 CE# A A DQ10 DQ11 DQ12 DQ13 NC DQ14 DQ15 DQ16 DQ17 DQ18 MODE A A A A A1 A0 88 89 92 93 94 97 98 99 100 8 9 12 13 14 18 19 22 23 24 31 32 33 34 35 36 37 4H 4K 6B 5L 3G 2B 4E 3A 2A ID 2E 2G 1H 5R 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
A A A A A A A MOE# DEN# MATCH DQ1 DQ2 DQ3 DQ4 ZZ DQ5 DQ6 DQ7 DQ8 DQ9 A A A ADV# ADSP# ADSC# OE# BWE#
44 45 46 47 48 49 50 51 52 53 58 59 62 63 64 68 69 72 73 74 80 81 82 83 84 85 86 87
2R 2T 3T 5T 6R 3B 5B 6P 7N 6M 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M
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100 Pin TQFP Package Dimensions
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
16.00 + 0.10 14.00 + 0.10
#1
20.00 + 0.10
22.00 + 0.10
1.40 + 0.05
1.60 Max Note: All dimensions in Millimeters
0.65 Basic
0.30 + 0.08
0.60 + 0.15
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7 x 17 (119-lead) BGA Dimensions
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
22.00 + 0.20 20.32 1.27
7 6
14.00 + 0.20
5
7.62
4 3 2 1
1.27
UT R P NML KJ
HGFEDCBA
o 0.75+0.15 (119X)
BOTTOM VIEW
19.50 + 0.10
12.00 + 0.10
0.70 REF.
0.90 + 0.10
30 TYP.
0.56 REF.
0.60 + 0.10
SIDE VIEW
Note: All dimensions in Millimeters
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2.40 MAX.
PIN 1A CORNER
TOP VIEW
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Ordering Information
GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM
GVT 71256T18 X - X
Galvantech Prefix Part Number Speed (6 = 3.5ns access/6.0ns cycle 6.7 = 3.8ns access/6.7ns cycle, 7.5 =4.0ns access/7.5ns cycle, 10 = 4.5ns access/10ns cycle) Package (T = 100 PIN TQFP B = 119 LEAD BGA)
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Rev. 8/98

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